1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to data processing systems using register renaming whereby register specifiers of an architectural set of registers are mapped to register specifiers of a physical set of registers.
2. Description of the Prior Art
Register renaming is a known technique for assisting in the support of out-of-order processing. Such systems are typically aimed at high performance applications where reducing gate count and reducing power consumption are not predominant considerations.
A problem arises with register renaming techniques when handling program instructions which reference a large number of registers each requiring renaming. The mechanisms necessary to support renaming of a large number of registers at one time require a disadvantageously large gate count and an associated disadvantageously large power consumption. Furthermore, once the renaming mechanism has renamed the registers then all of these renamed register specifiers must be passed in parallel along an instruction pipeline to the units which will utilise them. The passing of such a large number of renamed register specifiers in parallel along the instruction pipeline also requires a disadvantageous gate count and area penalty with an associated disadvantageous increase in the power consumption. Whilst the above problems may not be significant in systems in which gate count, area and power consumption are not particular constraints, they do represent a significant problem in the context of small, inexpensive and power efficient processors in which it is desired to keep the gate count, area and power consumption low.
An alternative to the above would be to stall an instruction requiring a large number of register renaming operations so that these could be accomplished over several processing cycles. However, this would disadvantageously stall the following program instructions and would still require the renamed register specifiers to be passed in parallel across a disadvantageously broad path along the pipeline once they have been generated.